These teachings relate generally to Pulse Width Modulators PWMs), and, more particularly, to Digital Pulse Width Modulators (DPWMs).
In high power applications, the PWM output is typically used to control large semiconductor switch devices, which have relatively long turn on and turn off times. One of the problems this causes is imposing a minimum and maximum duty cycle that may be realistically achieved before the resulting switch condition is constant off or on. This is referred to min/max Ton time and affects regulation ability near its limits. What is desired is a way to increase the DPWM resolution around these conditions without creating discontinuities harming overall performance.
All electronic devices emit radio frequency interference. It is a requirement that such devices pass FCC testing to ensure proper operation with other devices. It is desired to provide for a mechanism to improve compliance to EMI standards.
In typical multi-phase PWM applications, it is required that all PWM circuits be frequency locked such that they may occur at regularly predicted intervals. This permits optimal efficiency during operation. It is desired to have a mechanism to lock DPWM circuits together and pass important relationship information between them.